Subhead: Intel 18A-P enters risk production, delivering higher performance, enhanced thermal characteristics, and seamless design rule compatibility with Intel 18A.

RIYADH, Saudi Arabia – June 17, 2026 – At the 2026 VLSI Symposium, Intel Foundry provided a comprehensive update on its process technology roadmap and long-term innovation pipeline. The company announced that Intel 18A‑P, the first performance-enhanced node in the Intel 18A family, has successfully entered risk production, strictly meeting the production timeline shared with customers and ecosystem partners last year.

“Our updates and presentations at VLSI signal to Intel Foundry customers and partners that we are fully committed to leading-edge process innovation over the long term,” said Naga Chandrasekaran, Executive Vice President and General Manager of Intel Foundry. “This is a journey, and while we have more work ahead, we appreciate the opportunity to share the steady progress we are making with Intel 18A-P and our longer-range R&D.”

Key Intel 18A‑P Technical Advancements

Intel Foundry achieves the performance, power, and design benefits of Intel 18A-P through a highly optimized mix of transistor, interconnect, and design-technology co-optimizations (DTCO). During the symposium, engineering teams detailed several foundational breakthroughs:

• Power & Performance Gains: Intel 18A-P delivers a 9% performance uplift at iso‑power, or an 18% power reduction at iso-performance compared to Intel 18A, alongside enhanced thermal characteristics and design flexibility.
• Power Boost Technology: Unveiled as a new dual-contact, low-resistance transistor option, Power Boost enables higher drive current and increased frequency capabilities at matched capacitance.
• Thermal & Via Resistance Efficiency: Achieved a 20–40% improvement in thermal resistance via material and design innovations, paired with a 10–30% improvement in via resistance (the vertical connections between chip layers) utilizing geometric optimizations.
• Mobility & Fine-Tuning Options: Enhanced mobility via PMOS strain engineering for more efficient transistor current flow. Additionally, a new fifth logic $V_t$ pair between ULVT and LVT provides chip designers with greater precision when balancing speed and power.
• Seamless IP Reuse: Intel 18A‑P is fully design rule compatible with Intel 18A, allowing design teams to seamlessly reuse existing IP blocks and design flows. Similar to Intel 18A, it retains two cell heights (180nm and 160nm) and a contacted poly pitch of 50nm.

Validating GAA and Backside Power Architecture

Having successfully commercialized gate-all-around (GAA) transistors and backside power delivery (BSPD) with Intel 18A last year, Intel Foundry showcased how these architectures form the bedrock for next-generation logic scaling:

• Area & Voltage Droop Reductions: Intel Foundry Vice President and Fellow Eric Karl demonstrated a 11% routed area reduction and a 10X dynamic voltage droop reduction. This enables up to a 6% frequency uplift or greater than 15% dynamic power savings compared to standard frontside interconnect technologies.
• Silicon Real-World Success: Manju Shamanna from the Silicon and Platform Engineering group shared proven silicon results from CPU cores built on GAA and BSPD processes. The research highlighted robust frequency scaling at low voltages, including a ~30% frequency enhancement at low voltage (~0.5V), alongside reduced IR drop for highly efficient operation.

Next-Generation Silicon Scaling Research

Looking further into the future of semiconductor scaling, Intel Foundry highlighted three forward-looking R&D milestones:

1. CFET (Complementary FET): Demonstrated monolithic CFET inverters featuring vertically stacked NMOS and PMOS devices at a 45nm gate pitch, paving the clear architectural path beyond GAA.
2. GaN + Si Integration: Successfully showcased the 300mm monolithic integration of gallium nitride (GaN) power devices with silicon logic (including a ~1,000 gate digital control block), shrinking system complexity by housing high-performance power and digital control on a single process.
3. Subtractive Ruthenium Interconnects: Demonstrated subtractive ruthenium integrated with airgaps, yielding a ~35% capacitance reduction and distinct frequency advantages over traditional copper at tightly scaled dimensions.

To review the full catalog of Intel Foundry’s technical presentations at the event, please visit the official Intel Foundry portal.

This release contains forward-looking statements that involve a number of risks and uncertainties. Words such as “accelerate”, “achieve”, “aim”, “ambitions”, “anticipate”, “believe”, “committed”, “continue”, “could”, “designed”, “estimate”, “expect”, “forecast”, “future”, “goals”, “grow”, “guidance”, “intend”, “likely”, “may”, “might”, “milestones”, “next generation”, “objective”, “on track”, “opportunity”, “outlook”, “pending”, “plan”, “position”, “possible”, “potential”, “predict”, “progress”, “ramp”, “roadmap”, “seek”, “should”, “strive”, “targets”, “to be”, “upcoming”, “will”, “would”, and variations of such words and similar expressions are intended to identify such forward-looking statements, which may include statements regarding: Our Intel 18A-P process node and risk production of such node, including the performance, power and design benefits, competitiveness and technological advancements; Our research developments in CFET inverters, GaN + Si Integration and sRu interconnects.

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